Methods using disposable and permanent films for diffusion and implantation doping

ABSTRACT

Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.

BACKGROUND OF THE INVENTION

[0001] 1. Technical Field

[0002] This invention relates to the field of semiconductor processing.More specifically, the invention relates to methods using disposable andpermanent films to dope underlying layers through diffusion and usingdisposable films during implantation doping.

[0003] 2. Background Art

[0004] When doping semiconductor layers, and in particular source anddrain regions for Metal Oxide Semiconductor Field Effect Transistors(MOSFETs), ion implantation methods followed by an activation anneal aregenerally used. Ion implantation causes quite a bit of imperfections anddefects in the silicon structure. To activate the implanted dopants,high temperature (>900° C.) annealing is performed. This allows theimplanted dopant atoms to migrate into proper crystal structures. Thehigher the activation temperature, the more implanted dopants areactivated. However, the defects created by ion implantation enhance thediffusion of dopants, and it is more difficult to form shallow and lowresistivity source/drain diffusions.

[0005] This enhanced diffusion associated with ion implantation isparticularly detrimental when forming extensions. Extensions are shallowdoped areas, in the source and drain regions of MOSFETs, that connectthe device channel to the deeper source and drain diffusions. When theMOSFET's size is reduced, it is beneficial to scale the extensions to asshallow as possible to reduce short channel effects (while stillallowing silicide to be formed in the deeper source and drain diffusionregions), and to dope the extensions as high as possible to reducedevice series resistance.

[0006] What is needed are methods for doping underlying semiconductorlayers without enhancing the dopant diffusion during an activationanneal. These methods should also allow extensions to be formed withvery thin extensions to provide better junctions, yet allow adequatecontrol over the extensions' doping. Additionally, these methods shouldallow for layers used for doping that can subsequently be removedwithout damaging the remaining structure.

DISCLOSURE OF INVENTION

[0007] According to the present invention, methods are provided that usedisposable and permanent films to dope underlying layers throughdiffusion. Additionally, methods are provided that use disposable filmsdoped by ion implantation. Some of these disposable films can be createdfrom a traditionally non-disposable film.

[0008] The methods using removable or non-removable films to createshallow extensions use implantation doping to dope the removable film.During one or more anneal steps, the dopants diffuse from the removableor non-removable film and into the substrate. Methods usingtraditionally non-disposable films function by creating a water-solublefilm from a film that originally is not water-soluble.

[0009] The advantages of this invention are very little or noimplantation damage during the creation of the extensions, which enablesformation of very shallow extensions. The latter is a very importantadvantage of the present invention, particularly because, as transistorsare scaled smaller, extensions must be scaled proportionately to thetransistor size. Additionally, preferred removable films are preferablyremoved with solvents that will not etch or attack substrate materials(such as silicon) or other films (such as silicon dioxide orpolysilicon).

[0010] The foregoing and other features and advantages of the presentinvention will be apparent from the following more particulardescription of preferred embodiments of the invention, as illustrated inthe accompanying drawings.

BRIEF DESCRIPTION OF DRAWINGS

[0011] Preferred embodiments of the present invention will hereinafterbe described in conjunction with the appended drawings, where likedesignations denote like elements, and:

[0012] FIGS. 1-8 are cross-sectional views of successive processingsteps for forming a CMOS device, having very shallow extensions, inaccordance with a preferred embodiment of the present invention;

[0013] FIGS. 9-13 are cross-sectional views of successive processingsteps for forming a CMOS device, having very shallow extensions, inaccordance with a preferred embodiment of the present invention;

[0014]FIG. 14 is a cross-sectional view of a processing step forremoving sidewall spacers in accordance with a preferred embodiment ofthe present invention; and

[0015]FIG. 15 is a cross-sectional view of a processing step forremoving a conformally deposited film in accordance with a preferredembodiment of the present invention.

BEST MODE(S) FOR CARRYING OUT THE INVENTION

[0016] As discussed above, needs existed to provide methods for reducingthe damage created when doping the extensions of Metal OxideSemiconductor Field Effect Transistors (MOSFETs), for more adequatelycontrolling the depth of doping the extensions, and for providing easilyremovable films. Also, a need existed to reverse the order of deepsource/drain diffusion formation and the extension formation so that theextension activation anneal is independent of the deep source/draindiffusion activation anneal. The current invention meets these needs bydoping the extensions of MOSFETs with either removable or non-removablefilms, using diffusion from solid dopant sources instead of ionimplantation doping for the extension formation, and providing methodsfor turning germanium films or germanium-rich silicon-germanium(Si_(x)Ge_((1−x)), with x less than or equal to 0.3) into water-solublegermanium dioxide or germanium-rich silicon-germanium dioxide,respectively. It should be noted that proper control of parameters andconditions when depositing Si_(x)Ge_((1−x)) will allow x to be less thanor equal to 0.3.

[0017] In preferred methods of the present invention, when creatingdisposable sidewall spacers or disposable conformal layers, germaniumdioxide, germanium, or germanium-rich Si_(x)Ge_((1−x)) may be used. Ifgermanium or germanium-rich Si_(x)Ge_((1−x)) is used for these purposes,the germanium is turned into water-soluble germanium dioxide, or thegermanium-rich Si_(x)Ge_((1−x)) is turned into germanium-richsilicon-germanium dioxide, by placing the semiconductor wafer in anoxidizing atmosphere at a certain temperature range for a particulartime. Preferably, the oxidizing atmosphere is a plasma containingoxygen, as this allows for a lower temperature range. These steps shouldturn the germanium or germanium-rich Si_(x)Ge_((1−x)) into water-solublegermanium-rich silicon-germanium dioxide. The germanium dioxide orgermanium-rich silicon-germanium dioxide is then removed by dipping thesemiconductor wafer into water. Using water as a solvent is beneficialbecause water will not etch underlying layers of substrate or films.

[0018] It should be noted that for germanium-rich Si_(x)Ge_((1−x)) the xshould be less than or equal to 0.3. If this is the case, oxidizing thesilicon-germanium will allow an amorphous silicon oxide-germanium oxideto be formed that will be removable. This is primarily true because thesilicon will usually be bound to oxygen that is itself bound togermanium. Moreover, any germanium oxide should surround be fairly wellinterspersed between silicon oxide. If the germanium level is too low,however, the germanium oxide will be surrounded by silicon dioxide andmay not be soluble. Thus, it is preferred that the x in Si_(x)Ge_((1−x))be less than or equal to 0.3.

[0019] When using germanium dioxide for either the disposable sidewallspacers or disposable conformal layers, it can be beneficial to apply aprotective layer on top of the germanium dioxide. This is true becauseduring photoresist develop, some of the germanium dioxide may beremoved. Therefore, a protective layer, such as an anti-reflectivecompound or thin conformal film, may be added to protect the germaniumdioxide from the photoresist developer. This protective layer can thenbe removed after processing.

[0020] The conformally deposited removable layers, in preferredembodiments of the present invention, may be doped with the appropriatedopants in order to use diffusion doping to create source and drainregions. Generally, the removable layers will be doped through ionimplantation. Alternatively, the removable layer may be in situ dopedwhen the film is deposited by Chemical Vapor Deposition (CVD), insteadof doping through ion implantation. An anneal of the semiconductor wafercauses the diffusion from the removable conformal layer into underlyinglayers. It is preferable that the removable conformal layer be dopedwith n-type dopants prior to being doped with p-type dopants. Thissequence of steps allows a relatively short anneal step after theremovable conformal layer has been doped with n-type dopants, whichallows a longer total anneal time for the slower-diffusing n-typedopants, such as Arsenic (As). By doping the removable conformal layersthrough ion implantation or in situ doping and using them todiffusion-dope the underlying layers, very shallow extensions may bemade. These extensions can be made very thin by adjusting parameters ofthe process. Additionally, if ion implantation doping is used, verylittle or no damage to the silicon substrate is caused because dopantions are implanted mostly into the removable conformal areas. Prior artmethods used ion implantation to dope the extensions (or doped theextensions and then performed deep implantation of the source and drainregions), which caused defects in the substrate of the semiconductorwafer.

[0021] An example of a prior art method that is flawed is Japanesepatent 8,312,605, assigned to OKI Electric Ind. Co., Ltd., dated Aug.20, 1996. In this patent, the inventors disclose depositing a layer ofin situ boron-doped germanium or silicon-germanium onto a substratecontaining a gate. They then anneal the wafer to drive boron into thesubstrate to form p+ extensions. They directionally etch the conformallayer to form the spacer and then perform ion implantation of the deepsource/drain regions. An anneal is performed to activate the dopants.

[0022] A detriment to this method is that the extensions will be muchdeeper than desired. The anneal to activate the deeply implantedsource/drain dopants also drives the extensions in deeper. Additionally,the defects created by the source and drain implant enhance thediffusion of the extension dopant during the anneal. Thus, theextensions cannot be made shallow enough. Finally, to remove the layerof silicon-germanium or germanium, the inventors use a mixture ofhydrofluoric acid (HF) and nitric acid (HNO₃). These acid solutionsattack silicon dioxide and silicon, and remove silicon dioxide fromisolation trenches or the edges of gate oxide and silicon from thesubstrate and polysilicon gate.

[0023] Another flawed method of creating extensions is shown in U.S.Pat. No. 5,710,054, to Gardner et al., issued on Jan. 20, 1998. In thispatent, the inventors disclose doping a polysilicon spacer material andusing this to diffusion dope the extensions. Since the polysiliconspacers cannot be removed without damaging the silicon substrate and thegate polysilicon, the polysilicon spacers are left on the wafer. Thisstructure is prone to defects shorting the gate to the diffusions,particularly when the gate and diffusions are silicided.

[0024] The preferred methods of the current invention have none of thedetriments of this prior art. In preferred embodiments of the presentinvention, the formation (ion implantation and anneal) of deepsource/drain regions occurs before the extensions are doped. In thismanner, the depth of the extension doping may be much more tightlycontrolled, and the depth of the extension doping is independent of thedepth of deep source/drain diffusions. Additionally, very little or noimplantation damage occurs because an overlying layer of material thatis used as a diffusion source to dope the extensions receives themajority of dopant ions caused by ion implantation. Finally, thematerials used both for the spacers that are used when implanting thesource/drain regions and for the doping source layer may be removedusing solvents that do not attack silicon or silicon dioxide. Thus, thecurrent invention overcomes the majority of the problems of the priorart.

[0025] The following figures detail preferred embodiments and methodsused to create Complementary Metal Oxide Semiconductor (CMOS) FieldEffect Transistors (FETs). Each MOSFET will have very shallowextensions, the shallow extensions formed with little or no implantationdamage. Thus, the preferred methods create shallow extensions andMOSFETs with very low resistivity and shallow junctions in theextensions. In these methods and the accompanying claims, the steps areonly illustrative and are not to be considered to be in order, unless anorder is necessary.

[0026] Referring now to FIG. 1, semiconductor wafer portion 100 has twowells 120, 125 in substrate 170. It is to be understood that waferportion 100 is part of a semiconductor, generally a semiconductor wafer(the entire wafer is not shown in the following figures). Well 120 is alight to medium doped p-well, while well 125 is a light to medium dopedn-well. These wells are usually separated from other wells under ShallowTrench Isolation (STI) regions 110. Gate dielectric 150 and gateconductor 140 are films that have already been patterned into gates.Generally, gate dielectric 150 is a thermally grown oxide, but could bea deposited nitride or other suitable deposited material. Usually, gateconductor 140 is a deposited polysilicon, but it could be any othersuitable conductive material. The polysilicon gates 140 have beencreated by etching with a patterned photoresist mask (not shown). Ifnecessary, halo implantation is made for each type of CMOS device withappropriate photoresist mask after the gate polysilicon etch (notshown). Sidewall spacers 135 are formed by conformally depositing amaterial, then anisotropically etching the material to remove materialson the horizontal surfaces but not on sidewalls or vertical surfaces.Generally, a Reactive Ion Etch (RIE) is used to etch material 135 andform spacers 135. However, any appropriate etch may be used.

[0027] A photoresist film 190 is deposited and patterned to cover area530 and expose area 330. An As (arsenic) or P (phosphorous) implantationis performed in the energy range of 10 kilo-electron volts (KeV) to 20KeV, to implant deep source and drain locations 130 to a high dose(illustratively, 1×10¹⁵ to 5×10¹⁵ ions/cm²). Material 135 is preferablyremovable, such as germanium dioxide (the proper type—amorphousgermanium dioxide—that is removable in water), polycrystalline oramorphous germanium (which can then be converted to the removablegermanium dioxide), or germanium-rich silicon-germanium(Si_(x)Ge_((1−x)), with x less than or equal to 0.3, which can beconverted to removable germanium-rich silicon-germanium dioxide). In thefollowing example, material 135 is amorphous germanium dioxide, whichcan be removed by dipping the wafer in water for a certain time. Thegermanium dioxide or germanium-rich silicon germanium dioxide ispreferably deposited by Chemical Vapor Deposition (CVD), by placing thewafer in an atmosphere of GeH₄ and oxygen at an elevated temperature, orby plasma CVD at lower temperature, or by Jet Vapor Deposition at roomtemperature.

[0028] As an optional but preferred step, a conformal protective film193 is formed over the substrate and under photoresist layer 190 toprotect spacers 135 from developer. Protective film 193 is particularlyuseful when spacers 135 comprise germanium dioxide, as germanium dioxidemay be removed by developer. Polysilicon or amorphous germanium andsilicon-germanium are less likely to be removed by developer, and shouldnot require a protective film. Preferably, conformal protective film 193is 50 nm of Anti-Reflective Coating (ARC) material, such as CD9 or CD11by Brewer Science of Rolla, Mo., or DUV3, by Shipley of Marlborough,Mass. The ARC over area 330 is preferably removed through dry etching.Protective film 193 may comprise other films, such as 10-20 nm of plasmaCVD silicon dioxide (SiO₂) or silicon oxynitride (SiON) or vapordeposited Parylene. If inorganic high temperature material such assilicon dioxide or silicon oxynitride is used for the protective layer,the layer may be kept during implantation and anneal process steps.

[0029]FIG. 1 thus shows the deep implantation of impurities to createdeep source/drain regions. In the example of FIG. 1, an NMOS FET isbeing created in area 330.

[0030] Turning now to FIG. 2, wafer portion 100 is shown afterphotoresist film 190 has been stripped off, and protective layer 193removed by dry etching. Additionally, photoresist film 180 has beenapplied and patterned to cover area 330 while leaving area 530 exposed.Again, as an optional but preferred step, a conformal protective film193 is formed over the substrate and under photoresist layer 180 toprotect spacers 135 from developer. Protective film 193 is particularlyuseful when spacers 135 comprise germanium dioxide, as germanium dioxidemay be removed by developer. Polysilicon or amorphous germanium andsilicon-germanium are less likely to be removed by developer, and shouldnot require a protective film. Preferably, conformal protective film 193is 50 nm ARC material. The ARC over area 530 is preferably removedthrough dry etching. Alternatively, if high temperature materials areused as protective film 193, protective film 193 may be left on duringimplantation and anneal process steps.

[0031] A high dose (illustratively, 1×10¹⁵ to 5×10¹⁵ ions/cm²) B (boron)implant is performed in an energy range of 1 to 5 KeV. The implantcreates source/drain regions 160, for a PMOS FET in area 530. After theimplantation, the wafer is annealed, usually at temperatures of about900° C. to 1200° C. and for a time of about one second to 5 minutes.This reduces the damage caused by implantation and activates thedopants. Additionally, the dopants diffuse somewhat through well 120 andcreate deeper, wider source/drain regions 130.

[0032] Referring now to FIG. 3, wafer portion 100 is shown afterphotoresist film 180 has been stripped, after protective layer 193 hasbeen removed through dry etching, and after sidewall spacers 135 havebeen removed. When material 135 is germanium dioxide, the germaniumdioxide is removed by dipping in water. A layer of removable material320 is conformally deposited over the surface of wafer portion 100.Removable material 320 is preferably between 50 nanometers (nm) and 200nm thick, most preferably about 100 nm thick. Removable material 320 inthis example is germanium dioxide, which is again deposited through CVD.Photoresist layer 310 has been applied and patterned to cover area 530and expose area 330.

[0033] As an optional but preferred step, a conformal protective film193 is formed over the substrate and under photoresist layer 310 toprotect removable material 193 from developer. Preferably, conformalprotective film 193 is 50 nm of ARC material. The ARC over area 330 ispreferably removed through dry etching. Alternatively, if a hightemperature material is used as protective film 193, protective film 193may be left on during implantation and anneal process steps.

[0034] A high dose n-type dopant implantation is performed to create n+doping in layer 320 of area 330. This implantation is preferablyperformed at a 45 degree to 60 degree angle (angles 5010), relative tothe surface of the semiconductor, to make sure that layer 320 isimplanted at locations 5020, which are the gate's bottom corners. Thisimplantation is preferably performed in an energy range where most(>60%) of the implanted dopant is implanted into layer 320. For example,for arsenic, an energy range of 100 to 200 KeV, at a 45 degree angledinput should implant the majority of dopants in a layer 320 of 100 nmthickness. The ideal situation in FIG. 3 is to implant dopants close tothe surface of source/drain regions 130, but not into source/drainregions 130. The present invention preferably reduces damages caused byimplantation, so using too high of an energy during implantation couldcase dopants to pierce layer 320 and enter source/drain regions 130. Thelatter is not desired. The thickness of layer 320, the material used,the dopant used, and the energy may be adjusted to ensure that themajority of dopants remain in layer 320 during ion implantation.

[0035] It should also be noted that in situ doping of layer 320 may beperformed. In in situ doping, all the dopants are in the layer 320.There is no ion implantation damage with this method.

[0036]FIG. 4 illustrates an optional anneal step. FIG. 4 is shown afterthe resist 310 has been stripped and protective coating 193 has beenremoved. It should be noted that, if a high temperature material is usedas protective film 193, protective film 193 may be left on duringimplantation and anneal process steps. Now that the removable material320 in area 330 is heavily doped with n-type dopants (such as As), it ispreferable that a short anneal be performed. The short anneal ispreferably performed because of the relatively slow diffusion rate ofarsenic, as compared to boron. The present methods are preferably usedto create both types of extensions, so additional steps will create p+extensions (using, for instance, B) in area 530. Because As diffusesslower than B, if the anneal times for both are the same, the extensionswill be different widths and depths. This could have undesirableeffects, such as not enough overlap of the n+ extension and gate, or toomuch overlap of the p+ extension. Thus, it is preferred that a shortanneal be performed before implanting p-type dopants.

[0037] The preferred anneal step of FIG. 4 creates small extensions 410in source/drain regions 130. The n-type dopants diffuse from the layer320 (preferably germanium dioxide in this example) into well 120 tocreate extensions 410. It should also be noted that deep source/drainregions 130, 160 will also be affected by this anneal and will diffusein width and depth.

[0038] Referring now to FIG. 5, wafer 100 is shown after the preferableanneal step of FIG. 4. Furthermore, protective layer 193 has been addedover the substrate, and photoresist film 510 has been added andpatterned to reveal area 530 while covering area 330. Protective layer193 is preferably removed over area 530 through dry etching.Alternatively, if a high temperature, inorganic material is used forprotective layer 193, it may remain during implantation and annealprocessing steps. Removable material 320 in location 530 is nowimplanted, preferably through a 45 to 60 degree angle (see angles5010)implantation to implant areas 5020, with p-type dopants (such as boron).Again, the implantation energy, thickness of layer 520, dopants, andremovable material 320 may be changed to ensure that the majority (>60%)of dopant is implanted into layer 320. For instance, for boron,implantation energies of 10 to 30 KeV, at 45 degree angled implantationshould place the majority of the dopants into layer 320 of 100 nmthickness.

[0039] Turning now to FIG. 6, an anneal step is performed. As shown inFIG. 6, photoresist film 510 and protective coating 193 have beenremoved prior to the anneal. This anneal is preferably performed at atemperature of 900 to 1200° C. for a time of one second to 5 minutes.These anneal conditions should create extensions 410 and 610. It shouldbe noted that times longer than the recited periods may cause too muchoverlapping between the extensions and the gate, resulting in loweredperformance. In this anneal, both n-type and p-type dopants diffuse intowells 120, 125, respectively. It should also be noted that deepsource/drain regions 130, 160 will also be affected by this anneal andwill grow slightly in width and depth.

[0040] Referring now to FIG. 7, wafer portion 100 is shown afterconformal layer 320 has been removed and another conformal layer 710 isdeposited. Removed conformal layer 320 in this example was germaniumdioxide, which was removed by immersion in water. Additionally, aconformal layer of material 710 has been deposited. In this example,material 710 is silicon dioxide or silicon nitride that will be used forsidewall spacers and that has been deposited through CVD. FIG. 8 showswafer portion 100 after anisotropic etch (preferably RIE) has beenperformed to remove material 710 from horizontal surfaces yet leavematerial 710 on vertical surfaces. Additionally, silicide areas 810(preferably cobalt silicide, although titanium silicide and othersilicides may be used) have been added by any technique known to thoseskilled in the art. As is known in the art, the silicide over thediffusion areas reduces series resistance from the diffusion contact tothe device channel. The silicide over the gate is to reduce wiringresistance of the poly-silicon gate.

[0041] Thus, the method of FIGS. 1-8 has created an NFET in location 330and created a PFET in location 530, each of these having extensions withvery shallow junctions and low resistivity.

[0042] Turning now to FIG. 9, FIG. 9 illustrates a wafer portion 900that is wafer portion 100 after FIGS. 1 and 2. In other words, ionimplantation has already been performed to form deep source/drainregions 130 and 160. In FIG. 3, a removable material 320 was conformallydeposited on wafer portion 100. Here, in contrast, a non-removablematerial 910 is deposited. Non-removable material 910 is,illustratively, silicon dioxide that is deposited through CVD.Photoresist film 920 has been deposited and patterned to expose area 930while leaving area 1130 covered.

[0043] A relatively low energy, angled (preferably between 45 and 60degrees, as shown by angles 5010) implantation of n-type (As or P)dopants is performed. This implantation dopes film 910 in area 930, andthe implantation is preferably angled to dope areas 5020. It ispreferred that the thickness of film 910 be about 50 to 200 nm, and thatthe energy of implantation be adjusted so that the majority of the doseis implanted in the film (higher energy for thicker film and lowerenergy for thinner film). Preferably, the implantation energy, dopanttype, non-removable material 910, and thickness of non-removablematerial 910 are chosen such that the majority (>60%) of dopants implantinto film 910.

[0044] Referring now to FIG. 10, an optional but preferred anneal in thecase of As dopants is performed. FIG. 10 is shown after photoresist film920 has been stripped. The anneal allows the As to diffuse into well 120to create extensions 1020. As previously explained, As diffuses moreslowly than B.

[0045] Turning now to FIG. 1, wafer portion 900 is shown after the n+extension has been partially formed and after photoresist film 1120 hasbeen applied and patterned to expose area 1130 while covering area 930.A relatively low energy implantation of p-type dopants is performed.This implantation preferably dopes film 910 (preferably silicon dioxidein this example) with p-type dopants, such as boron. In FIG. 12, ananneal is performed to drive dopants from film 910 into the underlyingsubstrate. In this case, the n-type dopants diffuse further into well120 to deepen and widen extensions 1020, and p-type dopants diffuse intowell 125 to create extensions 1220. It is preferred that extensions 1020and 1220 be approximately the same width and length.

[0046]FIG. 13 illustrates wafer portion 900 after photoresist film 1120is stripped, and an anisotropic etch is performed to remove layer 910from the horizontal surfaces while keeping the layer on the verticalsurfaces. This etch is preferably an RIE that creates sidewall spacers910. Sidewall spacers 910 are doped (as indicated in FIG. 13) from theprevious implantation steps. Silicide areas (composed preferably ofcobalt silicide, although titanium silicide or other silicides may beused) 1310 have been added. The silicide over the diffusion areasreduces series resistance from the diffusion contact to the devicechannel. The silicide over the gate is to reduce wiring resistance ofthe polysilicon gate.

[0047] Thus, the method of FIGS. 1-2 and 9-13 has created an NFET inlocation 930 and created a PFET in location 1130, each of these havingextensions with very shallow junctions and low resistivity.

[0048] Another alternate method is illustrated by FIG. 14. FIG. 14 showswafer portion 100 after FIGS. 1 and 2 have been performed. In theprevious discussion of FIGS. 1 and 2, material 135 was preferablygermanium dioxide that had been conformally deposited and isotropicallyetched to create sidewall spacers. In the current embodiment, material135 is poly-germanium, amorphous germanium, or germanium-richsilicon-germanium (Si_(x)Ge_((1−x)), with x less than or equal to 0.3)that has been conformally deposited, preferably through CVD, andisotropically etched, preferably by RIE. This creates sidewall spacers135. The photoresist patterning, photoresist stripping, deepimplantation, and anneal steps have been performed to create andactivate deep source/drain regions 130 and 160.

[0049] To remove the poly-germanium, amorphous germanium, orgermanium-rich silicon-germanium spacers 135, the semiconductor wafer isplaced in an oxygen-containing atmosphere at an elevated temperature orin a plasma-oxygen atmosphere (which allows lower temperatures to beused). Preferably the temperature range is 500-700° C., which should notdrive much diffusion. Most importantly, this temperature range shouldcause minimal oxidation of polysilicon 140 and the silicon substrate.Most preferably, the poly-germanium, amorphous germanium orgermanium-rich silicon-germanium is oxidized at the low end of 500-600°C. in a plasma-oxygen atmosphere. The plasma-oxygen atmosphere is usedto lower the temperatures to the most preferable, recited temperaturerange. This process should allow all poly-germanium or amorphousgermanium to be converted to germanium dioxide, or allow allgermanium-rich silicon-germanium to be converted to germanium-richsilicon-germanium dioxide. The dioxide can then be removed by placingthe semiconductor wafer in pure water. The process of oxidation anddissolution of GeO₂ may be repeated if necessary to remove all the Gefilm.

[0050] Additional processing to create extensions may be performed bydepositing a conformal layer of removable or non-removable material usedfor doping the extensions by thermal anneal. Such methods have beenpreviously shown. Alternatively, a less preferred method is to usenormal ion implantation to create the extensions. As previouslydiscussed, the method causes a deeper junction due to enhanced dopantdiffusion by the effects caused by ion implantation.

[0051] Turning now to FIG. 15, this figure illustrates another preferredembodiment having removable film 320. FIG. 15 shows wafer portion 100after extensions 610 and 410 have been created through doping film 320and through thermal anneal to create diffusion from film 320 into theunderlying layers. In terms of the method of FIGS. 1-8, FIG. 15 showswafer portion 100 after FIG. 6 and after photoresist layer 510 has beenremoved. In the method of FIGS. 1-8, removable material 320 waspreferably germanium dioxide. In this embodiment, layer 320 is apoly-germanium, amorphous germanium, or germanium-rich silicon-germanium(Si_(x)Ge_((1−x)), with x less than or equal to 0.3) layer depositedpreferably through CVD. To create a removable substance, wafer portion100 is placed in an oxygen-containing atmosphere at an elevatedtemperature. Preferably the temperature range is 500-700° C., whichshould not drive much diffusion. Most importantly, this temperatureranges should cause only minimal silicon oxidation. Most preferably, thepoly-germanium, amorphous germanium, or germanium-rich silicon-germaniumis oxidized at the low end of 500-600° C. in a plasma-oxygen atmosphereto keep the temperature range low yet provide a relatively highoxidation rate for the germanium. The plasma-oxygen atmosphere is usedto lower the temperatures to the most preferable, recited temperaturerange. This process should allow all poly-germanium or amorphousgermanium to be converted to germanium dioxide, or allow allgermanium-rich silicon-germanium to be converted to germanium-richsilicon-germanium dioxide. The dioxide can then be removed by placingthe semiconductor wafer in pure water.

[0052] Additional processing steps may be performed, as described above,to create NFET and PFET devices. Moreover, the preferred embodimentswere described with a bulk silicon substrate, but the similar processcan be applied to silicon-on-insulator or silicon-germanium substratefor the same benefits.

[0053] While the invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein without departing from the spirit and scope of theinvention. Accordingly, unless otherwise specified, any dimensions ofthe apparatus indicated in the drawings or herein are given as anexample of possible dimensions and not as a limitation. Similarly,unless otherwise specified, any sequence of steps of the methodindicated in the drawings or herein are given as an example of apossible sequence and not as a limitation.

1. A method comprising the steps of: a) depositing a layer comprisinggermanium onto a substrate of a semiconductor wafer; b) heating thesemiconductor wafer in an oxygen atmosphere at a temperature above 500degrees centigrade wherein the germanium in the layer is converted intowater-soluble germanium dioxide; and c) removing the layer by placingthe semiconductor wafer in water.
 2. The method of claim 1 wherein thestep of heating the semiconductor wafer in an oxygen atmospherecomprises the step of heating the semiconductor wafer in an oxygenatmosphere at a temperature range of between 500 and 700 degreescentigrade.
 3. The method of claim 2 wherein the step of heating thesemiconductor wafer in an oxygen atmosphere comprises the step ofheating the semiconductor wafer in a plasma comprising oxygen at atemperature range of between 500 and 600 degrees centigrade.
 4. Themethod of claim 1 wherein the step of depositing a layer comprisinggermanium onto a semiconductor wafer comprises the step of depositinggermanium through chemical vapor deposition.
 5. The method of claim 1wherein the step of depositing a layer comprising germanium onto asemiconductor wafer comprises the step of depositing Si_(x)Ge_((1−x))through chemical vapor deposition under conditions wherein x is lessthan or equal to 0.3.
 6. The method of claim 1 further comprising thesteps of: d) forming a gate oxide over the substrate; e) depositing andpatterning at least one gate layer to create a gate, the patterningcreating two exposed substrate regions on opposing sides of the gate;and f) patterning the layer comprising germanium to form sidewallspacers on sidewalls of the gate.
 7. A method for making a transistor ona substrate of a semiconductor wafer, the method comprising the stepsof: a) forming a gate oxide over the substrate; b) forming at least onegate layer over the gate oxide; c) patterning the at least one gatelayer and the gate oxide to create a gate, the patterning creating twoexposed substrate regions on opposing sides of the gate; d) forming andpatterning a conforming layer to form decomposable sidewall spacers onsidewalls of the gate; e) implanting exposed portions of thesemiconductor wafer with a dopant of a first type to implantsource/drain regions in the substrate; f) heating the substratesufficiently to anneal and activate the dopant to further form thesource/drain regions; g) removing the decomposable sidewall spacers; h)forming a second conforming layer over the gate and source/drainregions; i) doping the second conforming layer with a dopant of thefirst type; j) heating the substrate at a temperature high enough tocause diffusion of the dopant of the first type from the conforminglayer and into underlying layers, thereby creating extensions in thesource/drain regions; and k) removing at least a portion of the secondconforming layer to expose at least the source/drain regions.
 8. Themethod of claim 7 wherein the step of forming a second conforming layerover the gate and source/drain regions comprises the step of forming thesecond conforming layer to a thickness of between 50 and 200 nanometers.9. The method of claim 7 wherein the step of doping the secondconforming layer with a dopant of the first type comprises the step ofimplanting the second conforming layer with a dopant of the first typehaving an energy, wherein a higher dopant energy is chosen with athicker second conforming layer and a lower dopant energy is chosen witha thinner second conforming layer, the step of implanting performedwherein the dopant impinges a surface of the semiconductor at anglesranging between 45 and 60 degrees.
 10. The method of claim 7 wherein thestep of doping the second conforming layer with a dopant of the firsttype comprises the step of performing in situ doping of the secondconforming layer.
 11. The method of claim 7 wherein the step of removingat least a portion of the second conforming layer to expose at least thesource/drain regions comprises the step of patterning the secondconforming layer to form sidewall spacers on the sidewalls of the gateand to expose the source/drain regions.
 12. The method of claim 11wherein the second conforming layer comprises silicon dioxide andwherein the step of forming a second conforming layer over the gate andsource/drain regions comprises the step of depositing through chemicalvapor deposition silicon dioxide over the gate and source/drain regions.13. The method of claim 7 wherein the step of forming and patterning aconforming layer to form decomposable sidewall spacers on sidewalls ofthe gate comprises the step of depositing the conformal layer comprisinggermanium.
 14. The method of claim 13 wherein the germanium is depositedthrough chemical vapor deposition.
 15. The method of claim 13 whereinthe step of removing the decomposable sidewall spacers comprises thesteps of: I) heating the substrate in an oxygen atmosphere at atemperature above 500 degrees centigrade wherein the germanium in thedecomposable sidewall spacers is converted into water-soluble germaniumdioxide; and II) removing the decomposable sidewall spacers by placingthe substrate in water.
 16. The method of claim 15 wherein the oxygenatmosphere is a plasma comprising oxygen and the temperature above 500degrees centigrade is a temperature between 500 and 600 degreescentigrade.
 17. The method of claim 7 wherein the step of forming andpatterning a conforming layer to form decomposable sidewall spacers onsidewalls of the gate comprises the step of depositing a conformal layerthat comprises Si_(x)Ge_((1−x)), wherein x is less than or equal to 0.3.18. The method of claim 17 wherein the Si_(x)Ge_((1−x)) is depositedthrough chemical vapor deposition and under conditions wherein x is lessthan or equal to 0.3.
 19. The method of claim 17 wherein the step ofremoving the decomposable sidewall spacers comprises the steps of: I)heating the substrate in an oxygen atmosphere at a temperature above 500degrees centigrade wherein the germanium in the decomposable sidewallspacers is converted into water-soluble germanium dioxide; and II)removing the decomposable sidewall spacers by placing the substrate inwater.
 20. The method of claim 7 wherein the step of forming andpatterning a conforming layer to form decomposable sidewall spacers onsidewalls of the gate comprises the step of depositing a conformal layerthat comprises germanium dioxide or Si_(x)Ge_((1−x)), wherein x is lessthan or equal to 0.3.
 21. The method of claim 20 wherein the step ofremoving the decomposable sidewall spacers comprises the step ofremoving the decomposable sidewall spacers by placing the substrate inwater.
 22. The method of claim 20 wherein the step of forming andpatterning a conforming layer to form decomposable sidewall spacers onsidewalls of the gate comprises the steps of: I) depositing germaniumdioxide or Si_(x)Ge_((1−x)), wherein x is less than or equal to 0.3,through chemical vapor deposition; and II) anisotropically etching theconforming layer.
 23. The method of claim 20 wherein: the method furthercomprises, after the step of forming and patterning a conforming layerto form decomposable sidewall spacers on sidewalls of the gate, thesteps of: I) forming a protective layer over the gate and its twoexposed substrate regions on opposing sides of the gate; and II) formingand patterning a photoresist layer on the substrate that exposes thegate and its two exposed substrate regions on opposing sides of thegate; and the step of implanting exposed portions of the semiconductorwafer with a dopant of a first type to implant source/drain regions inthe substrate further comprises the steps of: I) removing thephotoresist layer; and II) removing the protective layer.
 24. The methodof claim 23 wherein the protective layer is selected from the groupconsisting essentially of anti-reflective coating, silicon dioxide,silicon oxynitride, or Parylene.
 25. The method of claim 7 wherein thesecond conforming layer comprises germanium dioxide or Si_(x)Ge_((1−x)),wherein x is less than or equal to 0.3.
 26. The method of claim 25wherein the step of removing at least a portion of the second conforminglayer to expose at least the source/drain regions comprises the step ofremoving the second conforming layer by placing the substrate in water.27. The method of claim 25 wherein: the method further comprises, afterthe step of forming a second conforming layer over the gate andsource/drain regions, the steps of: I) forming a protective layer overthe portion of the second conforming layer that covers gate and its twoexposed substrate regions on opposing sides of the gate; and II) formingand patterning a photoresist layer on the substrate that exposes theportion of the second conforming layer that covers the gate and its twoexposed substrate regions on opposing sides of the gate; and the step ofimplanting the second conforming layer with a dopant of the first typefurther comprises the steps of: I) removing the photoresist layer; andII) removing the protective layer.
 28. The method of claim 27 whereinthe protective layer is selected from the group consisting essentiallyof anti-reflective coating, silicon dioxide, silicon oxynitride, orparylene.
 29. The method of claim 7 wherein the step of forming a secondconforming layer over the gate and source/drain regions comprises thestep of depositing a second conformal layer that comprises germanium.30. The method of claim 29 wherein the germanium is deposited throughchemical vapor deposition.
 31. The method of claim 29 wherein the stepof removing at least a portion of the second conforming layer to exposeat least the source/drain regions comprises the steps of: I) heating thesubstrate in an oxygen atmosphere at a temperature above 500 degreescentigrade wherein the germanium in the second conformal layer isconverted into water-soluble germanium dioxide; and II) removing thegermanium dioxide and the second conformal layer by placing thesubstrate in water.
 32. The method of claim 31 wherein the oxygenatmosphere is a plasma comprising oxygen and the temperature above 500degrees centigrade is a temperature between 500 and 600 degreescentigrade.
 33. The method of claim 31 further comprising the steps of:l) forming a third conforming layer of silicon dioxide over the gate andsource/drain regions; and m) anisotropically patterning the thirdconforming layer to form sidewall spacers on sidewalls of the gate. 34.A method for making a transistor of a first type and a transistor of asecond type on a substrate of a semiconductor wafer, the methodcomprising the steps of: a) forming a gate oxide over the substrate; b)forming at least one gate layer over the gate oxide; c) patterning theat least one gate layer and the gate oxide to create a first and asecond gate, the patterning creating two exposed substrate regions onopposing sides of each gate; d) forming and patterning a conforminglayer to form decomposable sidewall spacers on sidewalls of the gates;e) forming and patterning a first photoresist layer to expose the firstgate and its associated exposed substrate regions while covering thesecond gate and its associated exposed substrate regions; f) implantingexposed portions of the semiconductor wafer with a dopant of a firsttype to implant first source/drain regions in the substrate; g) removingthe first photoresist layer; h) forming and patterning a secondphotoresist layer to expose the second gate and its associated exposedsubstrate regions while covering the first gate and the firstsource/drain regions; i) implanting exposed portions of thesemiconductor wafer with a dopant of a second type to implant secondsource/drain regions in the substrate; i) removing the secondphotoresist layer; j) heating the substrate sufficiently to anneal andactivate the first and second type dopants to further form the first andsecond source/drain regions; k) removing the decomposable sidewallspacers; l) forming a second conforming layer over the gates andsource/drain regions; m) forming and patterning a third photoresistlayer to expose the second conforming layer covering the first gate andthe first source/drain regions while the third photoresist layer coversthe second conforming layer covering the second gate and the secondsource/drain regions; n) doping the second conforming layer with adopant of the first type; o) removing the third photoresist layer; p)forming and patterning a fourth photoresist layer to expose the secondconforming layer covering the second gate and the second source/drainregions while the third photoresist layer covers the second conforminglayer covering the first gate and the first source/drain regions; q)doping the second conforming layer with a dopant of the second type; r)removing the fourth photoresist layer; s) heating the substrate at atemperature high enough to cause diffusion of the dopant of the firstand second types from the conforming layer and into underlying layers,thereby creating extensions in the first and second source/drainregions; and t) removing at least a portion of the second conforminglayer to expose at least the first and second source/drain regions. 35.The method of claim 34 further comprising: u) after the step of removingthe third photoresist layer, performing the step of heating thesubstrate at a temperature high enough to cause diffusion of the dopantof the first type from the conforming layer and into underlying layers,thereby creating a partial extension in the first source/drain region.36. The method of claim 34 wherein: the method further comprises, afterthe step of forming and patterning a conforming layer to formdecomposable sidewall spacers on opposing sides of each gate, the stepof forming a protective layer over the gate and substrate; and the stepof removing the second photoresist layer further comprises the step ofremoving the protective layer.
 37. The method of claim 36 wherein theprotective layer is selected from the group consisting essentially ofanti-reflective coating, silicon dioxide, silicon oxynitride, orParylene.
 38. The method of claim 34 wherein: the method furthercomprises, after the step of forming a second conforming layer over thegates and source/drain regions, the step of forming a protective layerover the gate, source/drain regions, and substrate; and the step ofremoving the fourth photoresist layer further comprises the step ofremoving the protective layer.
 39. The method of claim 38 wherein theprotective layer is selected from the group consisting essentially ofanti-reflective coating, silicon dioxide, silicon oxynitride, orParylene.